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Problem results
ProblemCourse & topicStatus
Instruction-set architecture and assembly semanticsComputer Architecture · Mixed review
—Instruction-set architecture and assembly semanticsComputer Architecture · Mixed review
—Datapath and control implementationComputer Architecture · Mixed review
—Datapath and control implementationComputer Architecture · Mixed review
—Pipelining, hazards, and speculationComputer Architecture · Mixed review
—Pipelining, hazards, and speculationComputer Architecture · Mixed review
—Caches, virtual memory, and memory hierarchyComputer Architecture · Mixed review
—Caches, virtual memory, and memory hierarchyComputer Architecture · Mixed review
—Caches, virtual memory, and memory hierarchyComputer Architecture · Mixed review
—I/O, interrupts, and concurrencyComputer Architecture · Mixed review
—I/O, interrupts, and concurrencyComputer Architecture · Mixed review
—I/O, interrupts, and concurrencyComputer Architecture · Mixed review
—Parallel architecture and performance limitsComputer Architecture · Mixed review
—Parallel architecture and performance limitsComputer Architecture · Mixed review
—Parallel architecture and performance limitsComputer Architecture · Mixed review
—ARCH:9923001Mathematical problem title
IsaComputer Architecture Problem Solving
Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—Instruction-set architecture and assembly semanticsComputer Architecture · Calculation
—Showing 24 of 315 matching problems.
beq x5,x6,-16 encodes 0xFE6288E3; the B-type immediate is 0x1FF0 = -16 and the target from PC 0x1000 is 0x0FF0, not 0x0FF4
sum_to(3) pushes four 16-byte frames 0x80000FF0,FE0,FD0,FC0, returns 0,1,3,6, and restores the original sp
Unsigned shift-add of 13*11 holds P+M*Q=143 for eight iterations; Q=0 is not an early stop
A 250ps multicycle clock does not beat a 750ps single-cycle clock on this mix: 75ns versus 101.25ns for 100 instructions
From SN, TTTNTTTN misses four times and ends in WT; the second pass misses only on the taken-to-not exits
T1 wakes the older add; it cannot restore the younger F2 map
Two dirty evictions and three fills: eighty bytes, no trailing flush
A TLB miss walks; a page fault does not install
FR-FCFS serves the open row first; aging must still free the closed one
Polling, interrupt, and DMA change winners with B; the unit is CPU cycles
A capacity-4 descriptor ring posts through wrap and publishes only after data
A nonpreemptive round-robin bus grants M0 then M1 then M2 and needs bounded bursts
Roofline time is the max of a compute ceiling and a bandwidth ceiling
False sharing ping-pongs one MESI line without being a data race
A 1024-value binary reduction is span 10 but 36 cycles and memory bound
A 16-bit instruction format is partitioned as follows, with bit 15 the most-significant bit: - bits `[15:12]` opcod…
A processor uses 32-bit little-endian memory and 32-bit instructions that are always aligned to a multiple of 4.
Consider the following addressing-mode definitions for a 16-bit data path.
A load-store ISA has 32-bit registers `x0`–`x31`, with `x0` hardwired to 0.
An ISA uses an expand-opcode scheme on 16-bit instructions.
A 32-bit PC-relative branch is encoded as: - bits `[31:25]` `imm[12|10:5]` - bits `[24:20]` `rs2` - bits `[19:15]`…
The following assembly fragment is executed on a machine with 32-bit registers `r0`–`r15`, `r0` hardwired to 0, and…
A 12-bit instruction word has the format ``` bits [11:9] opcode bits [8:6] rA bits [5:3] rB bits [2:0] rC ``` for e…
A machine has eight 16-bit registers `R0`–`R7` and a 16-bit program counter.